A III-Nitride heterojunction transistor built on a silicon substrate has at least two failure modes where an excess voltage applied between the drain and the gate can cause an avalanche effect. The first mode is usually fatal to the device and that occurs when the conductive path is along the AlGaN Barrier layer. The second failure mode is more tolerable and is from the GaN channel through the III-Nitride Buffer to a substrate.
III-Nitride Heterojunction field effect transistors normally breakdown in the interface between the barrier layer and the insulation or passivation layer between the gate and the drain, and usually results in the destruction of the transistor. This problem is partially solved by restricting the operating range of the transistor, including transients, to stay within the breakdown limit. Alternatively, the transistor may be designed to allow safe breakdown of the transistor. Other partial solutions include purposely selecting the passivation or insulation layer or adding field plates to reduce the electric field between the source and drain and increasing the breakdown limit.
Typical III-Nitride Heterojunction field effect transistors have been fabricated on insulating substrates such as SiC, or sapphire, which are not suitable for conducting the breakdown current, especially at high speed. Typically, the voltage drop across a silicon substrate is small compared to the breakdown voltage for both conductive and high-resistance silicon substrates. For the more difficult high-resistance silicon substrate case, the estimated voltage drop is less than 20 V across a 6000 ohm-cm, 600 mm thick silicon substrate with a breakdown current of 10 microA/mm of gate width.
Prior art emphasis has been to prevent breakdown though the buffer layer in order to increase the transistor breakdown voltage. The structures were designed for preventing buffer breakdown in the transistor. For example, a GaN on silicon design for Nitronex RF transistors has a thin buffer ˜1.5 micrometer that breaks down at 450V. The breakdown at the surface for this device is less than 200V. Consequently an overvoltage causes a breakdown at the surface which destroys the device. Prior art design emphasis has been to increase the buffer thickness and material quality to increase the buffer breakdown voltage. One technique in the prior art has used separate devices such as Zener diodes to protect transistors or circuit.
Other researchers have reported the linear increase in substrate breakdown voltage with buffer layer thickness. Furukawa [N. Ikeda et. al, “High Power GaN HFETs on Silicon Substrate,”, Furukawa Review, No. 34, p. 17-23, 2008] reported buffer breakdown voltage up to 1700 V with a slope of 326 V/micrometer. The substrate breakdown versus buffer thickness characteristic may be measured experimentally for each buffer design. The breakdown characteristic will depend on buffer parameters including III-Nitride composition and design (e.g., super lattice), buffer quality (e.g., growth temperature, and stoichiometry), and doping or trap concentration (e.g., carbon concentration).
There are prior disclosures affecting breakdown voltages in III-Nitride Heterojunction transistors, such as growing III-Nitride on conductive substrates to reduce field strengths in the gate region, including silicon substrates [e.g., U.S. Pat. No. 7,538,366 issued May 26, 2009]. There are prior disclosures adding a III-Nitride buffer layer under III-Nitride Heterojunction transistors, some for isolation [U.S. Pat. No. 6,534,801 issued Mar. 18, 2003]. There is a prior disclosure connecting a p-type GaN buffer layer beneath an HFET to reduce surface fields (RESURF) which improves gate-drain breakdown voltage [U.S. Pat. No. 6,100,549 issued Aug. 8, 2000] but without addressing breakdown to the substrate. In general, prior art designs a buffer layer to prevent voltage breakdown through the buffer layer [U.S. patent application Ser. No. 11/103,127, PatApp Publication 20060226413] rather than take advantage of it.